The present application relates to a method of forming a semiconductor structure. More particularly, the present application relates to a method of forming a semiconductor nanowire field effect transistor with reduced parasitic capacitance.
The use of non-planar semiconductor devices such as, for example, fin field effect transistors (FinFETs) and semiconductor nanowire FETs is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. A semiconductor nanowire with a partially or a totally surrounding gate is one ideal architecture for off-current reduction in sub-45 nm technologies. A gate-all semiconductor nanowire configuration enables to relax channel film thickness requirements for a target leakage control. Stacked semiconductor nanowires yield very high current levels per layout surface area overcoming the current limit imposed by a small width to pitch ratio. Despite providing very high current levels, prior art stacked semiconductor nanowires have a high parasitic capacitance associated therewith.